Our Customer:
Our client is a cutting-edge technology team focusing on AI compilers and high-performance computing. They develop advanced tools and frameworks that optimize machine learning workloads on modern CPU, GPU, and accelerator architectures.
Your tasks:
- Lead and perform Static Timing Analysis (STA) across full-chip complex SoCs.
- Drive timing closure and signoff methodologies, ensuring high-performance and reliable designs.
- Collaborate with backend, DFT, and integration teams to resolve timing, async, and high-frequency challenges.
- Mentor and guide engineers in best practices for STA and chip-level timing analysis.
- Support full backend flows from RTL to tape-out, including synthesis, floorplanning, place & route, CTS, EM/IR, and chip integration.
- Contribute to process improvements and methodology enhancements in STA and signoff flows.
Required Experience and Skills:
- BSc or MSc in Electrical Engineering, Computer Science, or related field.
- 8+ years of experience in VLSI backend (RTL-to-GDS).
- 5+ years of hands-on STA experience using PrimeTime or equivalent tools.
- Strong experience with full-chip STA on complex SoCs.
- Expert knowledge of timing closure, signoff methodologies, and high-frequency design considerations.
- Good understanding of DFT architecture and DFT-related timing issues.
- Knowledge of asynchronous timing concepts and verification.
- Familiarity with complete backend flows: synthesis, floorplanning, place & route, CTS, STA, EM/IR, and chip integration.
- English — Upper-Intermediate.
Would be a plus:
- Experience optimizing timing in high-speed or advanced-node designs.
- Hands-on mentoring of junior or mid-level engineers in STA best practices.
Working conditions
5-day working week, 8-hour working day, flexible schedule;
Remote work.